Firmware - IP Cores: Custom services, 
DDC, FFT, Polyphase, JPEG Compression
BuiltWithNOF

IP Cores and Custom Processing

Ultimately as we try to handle higher and higher data quantities and speeds we need a fast means of reducing, processing or analysing the data on the fly. This can be immediately after sampling from a digitizer or camera such as in a DDC, polyphase filter or JPEG compressor. Or it can be done just before storage - i.e. do we discard or store based on criteria in the data. Or once we have terabytes of data stored to disk perhaps we need to summarize large chunks for display in a graph, or do some processing before further analysis (FFT for example).

Whatever your exact requirements chances are that it would be faster to use an FPGA and Hybrid DSP use several in their systems. Please inquire if you are interested in either using our standard IP cores in a system or subsystem (including our PMC/XMC digitizers and waveform generators) or to use in third party hardware. Of course if you need a custom implementation then please also contact us.

Wideband Digital Down Convertor

FFT Core (IEEE-754 Floating Point and Fixed point)

Polyphase Filter Bank

JPEG Compression


Wideband Digital Down Converter

block_diagram_ddc_medium

A Digital Down Converter performs channel access functions in digital receivers. It is used for extracting a channel (frequency band) of interest in a wideband signal. 4DSP's wideband DDC core employs a quad DDC architecture to achieve ultra high performances. The core accepts up to 16-bit complex data and can process 1GSPS continuously. With a fully programmable architecture at all stages of the processing, this core combines flexibility and speed and can be for example used in combination with the dual-channel 1GSPS AD491 module.

Input stage
Four 16-bit complex samples can be loaded to the core in parallel at a rate of 250MHz, thus providing an input bandwidth of 1GSPS. The input gain, implemented using multipliers, is user programmable.

NCO
The Numerically Controlled Oscillator architecture comprises four sets of sine and cosine directly applied to the mixers.

Mixer stage
The core implements four mixers in parallel in order to keep up with the input rate. FIR filters, with user-programmable filter coefficients, process the data after the mixer stage. The output of the filters can be decimated by a factor in the range 4 to 256.

Output stage
The output data format is user programmable and ranges from 16 to 32 bits.

Customized DDC cores are available upon request.

This core can be implemented in the following family devices:
Xilinx Virtex II, Virtex II Pro, Virtex-4, Spartan3
Altera Stratix, Stratix II, Cyclone II

A fully functional VHDL testbench and Matlab functions are delivered along the wideband DDC core for simulation purposes and specific performance characterization.

 

 


IEEE-754 Floating Point FFT/IFFT IP core

The most efficient and fastest available FPGA IEEE-754 compliant FFT/IFFT Floating Point core in the world. Designed for high performance programmable devices from Xilinx and Altera, this core performs Fast Fourier Transforms ranging from 256 points to 1M points and is ideal for high precision spectral analysis, radar and video processing applications. Download a bit-true software model for 1D and 2D FFT.

Data formats

 * IEEE-754 Floating Point (32-bit float)
* 24-bit mantissa, 8-bit exponent, 2's complement
* 14-bit mantissa, 8-bit exponent, 2's complement
* Specific data format upon request.

Benchmark

FFT/IFFT length

Texas Instruments C6713

Single 4DSP FFT core

Quad 4DSP FFT core

256

12.3Ás

3.68Ás

920ns

512

27.3Ás

6.24Ás

1.56Ás

1024

60.2Ás

11.4Ás

2.85Ás

2k

132Ás

61.4Ás

15.32Ás

4k

287Ás

123Ás

30.75Ás

16k

621Ás

246Ás

61.5Ás

32k

1.34ms

492Ás

123Ás

64k

2.87ms

1.31ms

328Ás

128k

6.12ms

2.62ms

655Ás

256k

13.4ms

5.24ms

1.31ms

512k

58.1ms

10.5ms

2.63ms

1M

122ms

21ms

5.25ms

Radix-32 vs Radix-2

This core is designed around a radix-32 butterfly architecture. With equal performances, the memory resources and bandwidth required by our core are five times less than a design comprising five radix-2 cores in parallel (a floating point radix-2 implementation is currently the only alternative available on the market). At the system level, this means that a single-width PMC module used to perform long transforms with our core achieves the same level of processing performances as a radix-2 implementation spread over two 6U CompactPCI boards bundled with multiple FPGA devices and memories.

Smart IP solutions increase board efficiency and reduce the price of Digital Signal Processing systems!

Target devices

 * Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3
* Altera Stratix, Stratix II, Cyclone II

Device resources usage (Virtex-4)

Data format

Slices

Multipliers 18x18

Block RAMs

IEEE-754

 12234

40

36

24-bit mantissa

11910

40

36

14-bit mantissa

7444

10

36

The following graph displays the Signal to Noise Ratio of a Fast Fourier Transform performed over a 1024 points random vector with a 24-bit wide mantissa and 8-bit wide exponent. The software Discrete Fourier Transform was calculated using the FFTw functions.

SNR_1k_FFT

A fully functional VHDL testbench and bit-true Software development kit are delivered along the FFT/IFFT core for simulation purposes and specific performance characterization.

Up to four FFT cores in parallel can be implemented on the FM482 PMC/XMC.

 

 


Polyphase filterbank

The polyphase filterbank algorithm is a very efficient way to implement a uniformly distributed multi-channel filterbank using a Fast Fourier Transform. The functional diagram below shows a polyphase filterbank with 256 channels, continuously processing digitized samples coming from a 2GHz Analog-to-Digital converter.

The polyphase filterbank core is designed for 16 up to 4096 channels. Slower processing rates to better suit various requirements can be implemented. The data resolution ranges from 8-bit up to 24-bit. A floating-point version of the core is available upon request.

polyphase_anim

This core can be used for the following family devices:
Xilinx Virtex II, Virtex II Pro, Virtex-4, Spartan3
Altera Stratix, Stratix II, Cyclone II

A fully functional VHDL testbench and Matlab functions are delivered along the polyphase filterbank core for simulation purposes and specific performance characterization.

 


JPEG compression core

This JPEG compression algorithm for FPGA is based on the ISO/IEC 10918-1 standard. This intellectual property core can be implemented on the Xilinx Spartan 3, Virtex-II, and Virtex-4 FPGA families. Data is fed to the FPGA through a user selected interface and is compressed into a JPEG JFIF format.

Specifications

* Up to 500 frames/s
* Up to 2048 x 2048 images
* Up to 16-bit pixel resolution

JPEG algorithm

The core compresses data by leveraging configurable tables, i.e. quantization and Huffman tables and can be customized to meet end users' architecture specifications. The compression ratio, depending on the quantization and Huffman tables, can vary from 0 to 100.

jpeg_architecture

Target devices

 * Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3

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