IEEE-754 Floating Point FFT/IFFT IP core
The most efficient and fastest available FPGA IEEE-754 compliant FFT/IFFT Floating Point core in the world. Designed for high performance programmable devices from Xilinx and Altera, this core performs Fast Fourier Transforms ranging from 256 points to 1M points and is ideal for high precision spectral analysis, radar and video processing applications. Download a bit-true software model for 1D and 2D FFT.
Data formats
* IEEE-754 Floating Point (32-bit float) * 24-bit mantissa, 8-bit exponent, 2's complement * 14-bit mantissa, 8-bit exponent, 2's complement * Specific data format upon request.
Benchmark
FFT/IFFT length
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Texas Instruments C6713
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Single 4DSP FFT core
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Quad 4DSP FFT core
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256
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12.3µs
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3.68µs
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920ns
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512
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27.3µs
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6.24µs
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1.56µs
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1024
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60.2µs
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11.4µs
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2.85µs
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2k
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132µs
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61.4µs
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15.32µs
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4k
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287µs
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123µs
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30.75µs
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16k
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621µs
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246µs
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61.5µs
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32k
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1.34ms
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492µs
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123µs
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64k
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2.87ms
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1.31ms
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328µs
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128k
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6.12ms
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2.62ms
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655µs
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256k
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13.4ms
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5.24ms
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1.31ms
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512k
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58.1ms
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10.5ms
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2.63ms
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1M
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122ms
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21ms
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5.25ms
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Radix-32 vs Radix-2
This core is designed around a radix-32 butterfly architecture. With equal performances, the memory resources and bandwidth required by our core are five times less than a design comprising five radix-2 cores in parallel (a floating point radix-2 implementation is currently the only alternative available on the market). At the system level, this means that a single-width PMC module used to perform long transforms with our core achieves the same level of processing performances as a radix-2 implementation spread over two 6U CompactPCI boards bundled with multiple FPGA devices and memories.
Smart IP solutions increase board efficiency and reduce the price of Digital Signal Processing systems!
Target devices
* Xilinx Virtex-II, Virtex-II Pro, Virtex-4, Spartan-3 * Altera Stratix, Stratix II, Cyclone II
Device resources usage (Virtex-4)
Data format
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Slices
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Multipliers 18x18
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Block RAMs
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IEEE-754
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12234
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40
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36
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24-bit mantissa
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11910
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40
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36
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14-bit mantissa
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7444
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10
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36
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The following graph displays the Signal to Noise Ratio of a Fast Fourier Transform performed over a 1024 points random vector with a 24-bit wide mantissa and 8-bit wide exponent. The software Discrete Fourier Transform was calculated using the FFTw functions.
A fully functional VHDL testbench and bit-true Software development kit are delivered along the FFT/IFFT core for simulation purposes and specific performance characterization.
Up to four FFT cores in parallel can be implemented on the FM482 PMC/XMC.
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